1. Field of the Invention
This invention relates to the field of video processing and, in particular, to the compression and decompression of video signals.
2. Background Art Statement
It is well-known to provide hardware circuitry for performing video encoding and decoding operations. In particular, it is known to provide hardware circuitry to perform frame adds and frame subtracts, run length encoding and decoding, forward and inverse discrete cosine transforms, and quantization/dequantization operations as well as motion estimation and variable length encoding and decoding. When greater processing power was required or when improved algorithms became available in these systems, it was thus necessary to perform hardware redesign and provide new integrated circuit chips. These redesigns were very expensive and slow.
However, many of these operations were much too complex to be performed by software since executing software capable of performing these tasks would require too much time to be useful for video processing. An exception to this is the processing required for motion estimation. However, improvements in motion estimation methods still required extension hardware redesign since these operations were embedded in the overall hardware circuitry. The motion estimation process required a great deal of memory space because several different images had to be buffered. These images included a current image being encoded, the previous image, a companded image provided by decoding the data being encoded and transmitted, and the new digitized video data being received by the system. Thus four full size image buffers were required.
It is well known to perform loop filtering within video compression and decompression these systems. For example, it is known to provide a two-dimensional spatial filter which operates on pels within a predicted eight-by-eight block. The filter is separable into two one-dimensional functions, horizontal and vertical. Both the horizontal function and the vertical function are nonrecursive with coefficients of one-quarter, one-half and one-quarter except at block edges where one of the tags would fall outside the block. In such cases the one-dimensional filter is altered to have coefficients zero, one and zero. Full arithmetic precision is retained with rounding to eight bit integer values at the two-dimensional filter output.
In addition, it is well known to provide quantization within these systems. In a typical system the number of quantizations may be one for the intrablock encoded DC coefficient and thirty-one for all other coefficients. Within a macroblock the same quantization is used for all coefficients except the intrablock encoded DC quantization. The decision levels may not be defined. The intrablock encoded dc coefficient is nominally the transform value linearly quantized with a step size of eight and no dead zone. Each of the other thirty-one quantizations is also nominally linear but with a central dead zone around zero and with a step size of an even value in the range two to sixty-two. In these systems the full dynamic range of the transformed coefficients cannot be represented for smaller quantization step sizes.
To prevent quantization distortion of transformed coefficient amplitudes causing arithmetic overflow in the encoder and decoder loops, clipping functions are sometimes inserted. The clipping functions are applied to the reconstructed image which is formed by summing the prediction and the prediction error as modified by the coding process. This clipper operates on resulting pel values less than zero or greater than two hundred fifty-five, changing them to zero and two hundred fifty-five respectively.
Values that are quantized in this manner may be dequantized in the following manner. For all coefficients other than the intrablock encoded DC quantization the reconstruction levels, REC, are in the range of -2048 to 2047 and are given by clipping the results of the following equations:
REC=QUANT*(2*LEVEL+1); LEVEL&gt;0 QUANT="odd" PA0 REC=QUANT*(2*LEVEL-1); LEVEL&lt;0 QUANT="odd" PA0 REC=QUANT*(2*LEVEL+1)-1; LEVEL&gt;0 QUANT="even" PA0 REC=QUANT*(2*LEVEL-1)+1; LEVEL&lt;0 QUANT="even" PA0 REC=0; LEVEL=0
Where QUANT ranges from one to thirty-one. These reconstruction levels are symmetrical with respect to the sign of LEVEL except for the values 2047 and -2048.
In the case of blocks which are intrablock encoded the first coefficient is nominally the transform DC value linearly quantized with a step size of eight and no dead zone. The resulting values are represented with eight bits. A nominally black block provides the value 0001 0000 and a nominally white block yields 1110 1011. The codes 0000 0000 and 1000 0000 are not used. The reconstruction level of 1024 is coded as 1111 1111. Coefficients after the last non-zero one are not transmitted.
It is also know to provide both hardware and software forward and inverse discrete cosine transforms in these systems. When hardware is provided for this purpose space is wasted on the integrated circuit chip because only one transform is performed at a time. Thus space on the chip is always taken up by a transform circuit which is not in use.
It is common to perform these discrete cosine transforms using a number of multipliers and adders. For example it is known to perform an eight point fast discrete cosine transform in a single clock cycle using twelve multipliers and twenty-nine adders. It is also known to perform it in more clock cycles using less hardware. These different transform devices are useful for different applications. For example many high quality video applications require great speed and a great deal of space for transform hardware may be provided. In other applications, for example, video conferencing great speed is not required and it is preferred to provide more efficient use of hardware application.